This invention relates to binary multiplying systems, and more particularly to a 2's complement multiplying system of complex numbers.
Complex multipliers or equivalent logic circuits made up of multiplier and adder building blocks are used to perform vector rotation operations in filter sections of digital radar signal processors and of digital communication equipment. Frequently in these units and in other similar applications albeit low precision (4-12 bit) complex multiplications are performed at rates of 10.sup.6 - 10.sup.8 operations per second. Therefore, very high speed complex multiplier units which the present invention describes can be used in such filter sections to replace larger numbers of slower complex multipliers such as currently used thereby reducing equipment cost. In addition, the high speed complex multipliers can be used to effect improved processor performance.
In the prior art, complex multiplication has frequently been implemented in signal processors using adder and real multiplier building blocks. In some other processors, however, read only memory circuits are used in conjunction with special logic circuitry to effect complex multiplication or complex multiplication-like operations tailored to meet specific internal processor requirements. When read only memories or combinations of available integrated circuit multipliers and adders are used, the number of gating stages, and hence the time delay through the complex are larger than they are when the subject invention is used. Thus the subject invention permits a reduction in complex multiply time or equivalently an increase in the through-put rate of the processing equipment in which it is used.
The performance of complex multipliers built using discrete multipliers and adders depends on the performance of these discrete components and the method of interconnecting them. If prior art commercial MSI circuits and ICs were used to "build up" the component multipliers and adders, then an ensemble complex multiplier delay of .about.50 nsec would be required for a circuit performing the same operation as that performed by the complex multiplier disclosed herein. This assumes that ECL-10000class integrated circuit processing technology is used to fabricate the integrated circuits, and that these circuits are interconnected using multilayer printed circuit boards. If discrete small scale integrated universal logic gate (ULG) implemented adders and multipliers as are described in the present invention were used, however, complex multiplier propagation delay of .about.25 nsec could be achieved with multi-layer printed circuit board interconnection of these circuits.
The specific propagation delay through a complex multiplier in general depends on the performance of the devices such as transistors incorporated in the integrated circuit logic elements, the manner in which these elements are interconnected, and the number of gating stages in the complex multiplier network. On the assumption that a given integrated circuit processing technology is used to fabricate the integrated circuit logic elements, e.g, gates or cascode cells, then the delay through an individual gate or cascode cell will be approximately constant and the delay through the complete complex multiplier will depend only on the interconnection method and the number of stages in the network. In this regard, if current production ECL-10000 class processing is used, each gate or cascode cell will introduce a delay of approximately 2.5 - 3.5 nsec. However, if currently available dielectrically isolated ECL fabrication technology is used instead and if at the same time the gate or cascode cell circuits are designed for maximum speed, with correspondingly higher power dissipation, then each gate or cascode cell will introduce a delay of approximately 0.25 - 0.35 nsec. Moreover, in the future when electron beams are used to fabricate much smaller devices with dielectrically isolated technology, individual cell or gate delay may be further reduced, for example, to about 0.1 nsec.
The method of interconnecting the gate or cascode cell elements is a second factor strongly effecting the performance of a logic network such as a complex multiplier. If the cells or gates are built in small numbers as individual integrated circuit chips and these circuits are packaged and interconnected on printed circuit boards, the delay will be greater than if the individual chips are assembled, for example, in a single hybrid module. Still further, delay reduction will be achieved if the gates or cells are arranged on a small number of large scale integrated circuit dice. The delay reduction is achieved by reducing the length of the interconnection wiring between the cells or gates.
However, regardless of the integrated circuit fabrication technology and the method of interconnection, the subject invention permits reducing the delay through a complex multiplier logic network. This delay reduction is achieved because a new logic design is used which requires only a five gating stage ULG network implementation. Therefore the delay introduced by the additional, for example, five more gating stages in more conventional designs, and the delay introduced in the wiring to interconnect these additional stages is eliminated. The new logic design permitting these reductions is summarized next and then described in greater detail.